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電子開發(fā)工程師英文簡(jiǎn)歷表格
似乎對(duì)很多人來說，他們?cè)趯?shí)施簡(jiǎn)歷書寫時(shí)，都會(huì)非常關(guān)注簡(jiǎn)歷的外在效果，在很多人的認(rèn)知里，只有那些外在效果十分出眾的個(gè)人簡(jiǎn)歷，才能夠在遞交至招聘方手中受，吸引到他們的關(guān)注，并且在求職過程中增加就職的幾率性。但他們卻忽視了，太過于注重外在效果的個(gè)人簡(jiǎn)歷有時(shí)也并不一定可以發(fā)揮出對(duì)他們而言比較滿意的效果。因?yàn)檫@種簡(jiǎn)歷的制作往往會(huì)呈現(xiàn)出外在觀賞性效果強(qiáng)，而實(shí)際內(nèi)容卻不佳的水準(zhǔn)。
除了上面提及的問題之外，還有一點(diǎn)因素也是求職者必須有所關(guān)注的，那就是簡(jiǎn)歷的敘述意義。其實(shí)價(jià)值的衡量標(biāo)準(zhǔn)在于簡(jiǎn)歷的書寫理念。簡(jiǎn)歷本身是一種表達(dá)能力非常強(qiáng)的表達(dá)方式，所以我們必須要關(guān)注它的敘述意義。若失去了簡(jiǎn)歷能夠表達(dá)出來的運(yùn)用意義，那么簡(jiǎn)歷也很難凸顯出求職者的個(gè)人能力。
| Name： yjbys | Hukou：Shanghai | |||||
| Residency：Shanghai | Work Experience： | |||||
| Current Salary： | Tel： | |||||
| E-mail：www.ruiwen.com/jianli | ||||||
| Career Objective | ||||||
| Desired Industry： | Electronics/Semiconductor/IC ,Science/Research ,Government ,Others ,Testing, Certification | |||||
| Desired Position： | Senior Hardware Engineer ,Semiconductor Technology, Branch Office Manager ,Chief Representative ,Research Specialist Staff | |||||
| Desired address： | Shanghai ,Hongkong ,Beijing ,Taiwan ,Macao | Desired Salary： | Negotiable | |||
| Work Experience | ||||||
| 20xx/06—Present | ***Company | |||||
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Industry: Electronics/Semiconductor/IC Intel Flash Engineering Department Individual Contributor Responsibilities： I have been working in Intel Flash Assembly & Test Engineering Department as an Individual Contributor since June of 20xx. Being Leader of ATE Yield team, I have been working with the team members to improve the products yield. Our efforts are paid off:
Reference: Bao Powel Achievements: Being Leader of ATE Yield team, I have been working with the team members to improve the products yield. Our efforts are paid off:
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| 20xx/01—20xx/05 | Intel(Shanghai) Technology Development Ltd. Company | |||||
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Industry: Electronics/Semiconductor/IC Intel STTD-China Department Electronics Development Engineer Responsibilities：
Reference: Bao Powel Reason for Leaving: I was transferred to Intel（Shanghai）Products Ltd. Company due to the internal re-organization in June of 20xx. Achievements: As a main contributor of STTD-China department, I co-work with my colleagues to succeed in developing a set of MASSIVELY PARALLEL CLASS TEST equipment, which is able to test more than 6700 units in one cycle. |
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| 20xx/05—20xx/01 | Nanyang University of Science & Technology | |||||
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Industry: Electronics/Semiconductor/IC Electronics & Electrical Engineering Department Research Fellow Responsibilities：
Subordinate: 3 Reference: Patrick Low Reason for Leaving: I completed the project which I undertook by myself, and want to do more challenging job. Achievements: In less than one year, I made a lot of experiments and acquired the wonderful data for the project by myself. |
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| Project Experience | ||||||
| 20xx/01—Present | Assembly NPI (New Product Introduction) | |||||
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Project Description: To introduce more products into Intel Flash Assembly factory, I join Assembly NPI team and work as the team leader. I coordinate with IE, Planner, Marketing guy and Engineer to select new product items, do demo in factory, and then qualify it. Responsibility: I am working as NPI Team leader and coordinate all team members, define the NPI candidate, make Assembly build plan, follow up the progress. |
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| 20xx/01—20xx/12 | Marginal Electrical Boards Rescue | |||||
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Project Description: To rescue some electrical boards of testing equipment, a Task Force team was built up and led by me. We categorized each kind of board, made historical failure analysis on each kind of board and around &2.5 million dollars was saved finally. Responsibility: Being the team leader, I took the job of data analysis, define each member's role, make program plan, coordinate each team member and follow up the progress. |
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| 20xx/10—20xx/05 | Optimization the current Test Process Order for Flash Memory | |||||
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Project Description: To simplify the current Test procedure and enhance the working efficiency, a Task Force team has been called and started by me. Responsibility: Being the Project leader, I take the main responsibility, such as, design, plan, organize and implement. |
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| 20xx/05—20xx/12 | Test Yield of Flash memory Improvement | |||||
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Project Description: To improve the test yield of different products, a Task Force team was built up and led by me. Being the team leader, I worked with all team members to dig out the failure root cause for each product, defined action taken plan for each emergency case, coordinated each team member and make pro-active plan to avoided unexpected things happen. Responsibility: Being the team leader of Improving Test Yield, coordinate each team member, make program plan and follow up. |
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| Education and Training | ||||||
| 20xx/05—20xx/01 | Nanyang University of Science & Technology Microelectronics Doctorate | |||||
| I worked in Nan yang University of Science & Technology as a Research Fellow. I major at Gate oxide Reliability research in the duration. | ||||||
| 20xx/03—20xx/03 | Seoul National University of Korea Microelectronics Others | |||||
| I had been working in National Physical Lab of Seoul National University in Korea since March of 20xx to March of 20xx as a Post-doctor. Where I unhook the project of research & development of Carbon-Nan tube Biosensor. And only after one year, an EIS sensor based on CMOS technology has been successfully produced. And one SCI paper about it has been published in Semiconductor Science and Technology. | ||||||
| 20xx/03—20xx/03 | Shanghai Institute of Microsystems and Information Technology，Chinese Academy of Sciences Information Technology Doctorate | |||||
| 20xx/09—20xx/03 | Nanjing University of Science & Technology Material Science and Engineering Master | |||||
| Being a master student of this period, I have published one EI paper about Super-fine metal power's electrical characteristics. | ||||||
| 20xx/09—20xx/07 | Nanjing University of Science & Technology Material Science and Engineering Bachelor | |||||
| 20xx/07—20xx/07 | Assistant Engineer in Quality Verification Department, Boiler Factory in Zhengzhou city of Henan resistant Engineer in Quality Verification Department | |||||
| Professional Skills | ||||||
| Language Skills： |
English: EXCELLENT Korean: AVERAGE |
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| Computer Skills： |
Technology skilled 96Month SAP understanding 8Month |
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| Certificate： |
20xx/11 MCSE 20xx/06 CET6 |
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| Self-appraisal | ||||||
| 7 years working experience of Semiconductor Industry and where 2 years overseas working/study experience. Smart working, innovation thinking and very talented creative working model. | ||||||
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